1. Field of the Invention
This invention relates to logic circuits and particularly to such circuits employing CMOS components for converting a three-state digital signal into two two-state digital signals.
2. Description of the Prior Art
Monolithic integrated, complementary insulated-gate field-effect transistor technology, i.e., so-called CMOS technology, is described, for example, in the journal "The Electronic Engineer", May 1970, pp. 52 to 57. The basic building block of a CMOS circuit is the so-called CMOS inverter, i.e., a series combination of N-channel and P-channel transistors whose gates are interconnected and serve as the input to the inverter, whose output is the junction of the drain electrodes of the N-channel and P-channel transistors. The source electrode of the N-channel transistor is grounded, and that of the P-channel transistor is connected to a positive dc supply voltage. Both transistors are of the enchancement mode.
In the above reference, such circuits are called "complementary-symmetry MOS circuits", which indicates that the physical dimensions of the P-channel and N-channel transistors are such that, in the "on" state of the respective transistor, the resistance of the controlled current path is equal in both transistors. A measure of this on-resistance is the ratio of the channel width W to the channel length L, i.e., the so-called W/L ratio. To achieve the above-mentioned equality of the on-resistances of the two complementary transistors, for physical reasons the W/L ratio of the P-channel transistor must be about 1.5 times that of the associated N-channel transistor. In a low-resistance transistor, the W/L ratio must be large compared to unity.
Conventional CMOS circuits are particularly suitable for digital circuits which process binary signals, i.e., signals having two possible states. One state has a value which is virtually equal to the supply voltage level and is therefore designated "H", while the other has a value which virtually corresponds to ground potential and is therefore designated "L". Thus, if one of these two states is presented to the input of a CMOS inverter, the signal at the output of the inverter will change to the respective other state. In the case of symmetrical CMOS inverters, this change of state takes place when the input voltage is traversing the range of about one half the H-state voltage.